1. Field of the Invention
The present invention is directed in general to computer systems including cache memories including non-cacheable regions and, more specifically, to testing the functioning of the non-cacheable regions.
2. Description of the Related Art
In a computer system, the operating speed of the system processor is dependent upon the rate at which data can be exchanged between main memory and the processor. In an attempt to reduce the time required for the exchange of data between the processor and main memory, many computers include a cache memory placed between the processor and main memory. The cache memory, or cache, is a small, high-speed buffer memory that is used to temporarily store portions of the contents of main memory. In selecting which portions of the contents of main memory to store, a cache controller estimates which data will soon be requested by the processor. The increased access speed of the cache memory generally results in a reduction in the average time necessary for the processor to access data from main memory.
A cache memory consists of many blocks of one or more words of data. Each block has associated with it an address tag. Each address tag uniquely identifies a memory block stored in the cache directory. If the desired data is in the cache, the cache provides the data to the processor. If the desired memory block is not in the cache, the block of data containing the requested data is retrieved from the main memory, stored in the cache, and supplied to the processor.
In addition to using a cache to retrieve data from main memory, the processor may also write data into the cache. Data is written to the cache instead of writing the data directly to main memory, or, in a write-through cache, data is written to the cache concurrently with the writing of the data to the main memory. When the processor desires to write data to memory, the cache controller checks the cache directory to determine if the data block into which the data is to be written resides in the cache. If the data block exists in the cache, the processor writes the data into the data block in the cache. If the data block into which the data is to be written is not in the cache, the data block must be fetched into the cache or the data written directly into the main memory. However, the cache is transparent to the computer system, so determining the actual contents and functioning of the cache at any particular point in time is difficult. Specifically, any attempt to access the data in the cache is likely to result in a reallocation of the cache contents.
Certain spaces in main memory should not be cached, and the cache memory may be programmed to accommodate non-cacheable addresses for non-cacheable regions of the main memory. For example, portions of the main memory address range which are used as device inputs should not be cached especially in processors which don't differentiate between memory and I/O addresses. Should the processor be looping while awaiting a change in the status of a switch panel, for example, no change will be noticed if the first reading from the switch panel was cached. Some processors also use a portion of the main memory address range for communication with coprocessors. The data cannot be assumed to be static, so a cached copy might become out of date. Multiprocessor systems also often communicate via flags which are set and cleared in dedicated main memory locations. No communication can occur if the main memory flag that one processor sets cannot be read by another since the other is reading a cached copy. All of these example are reasons for accommodating non-cacheable addresses within the cache or non-cacheable regions within memory.